By Yoonjin Kim
Coarse-grained reconfigurable structure (CGRA) has emerged as an answer for versatile, application-specific optimization of embedded structures. aiding you recognize the problems desirous about designing and developing embedded structures, layout of Low-Power Coarse-Grained Reconfigurable Architectures deals new frameworks for optimizing the structure of parts in embedded platforms with the intention to lessen region and keep energy. genuine program benchmarks and gate-level simulations substantiate those frameworks. the 1st half the ebook explains how one can lessen strength within the configuration cache. The authors current a low-power reconfiguration method in response to reusable context pipelining that merges the idea that of context reuse into context pipelining. additionally they suggest dynamic context compression in a position to helping required bits of the context phrases set to let and the redundant bits set to disable. moreover, they talk about dynamic context administration for decreasing energy intake within the configuration cache through controlling a read/write operation of the redundant context phrases. concentrating on the layout of an economical processing aspect array to lessen region and gear intake, the second one half the textual content provides an economical array textile that uniquely rearranges processing parts and their interconnection designs. The publication additionally describes hierarchical reconfigurable computing arrays which include reconfigurable computing blocks with forms of verbal exchange constitution. the 2 computing blocks percentage serious assets, delivering an effective communique interface among them and lowering the general zone. the ultimate bankruptcy takes an built-in method of optimization that attracts at the layout schemes provided in past chapters. utilizing a case examine, the authors reveal the synergy impact of mixing a number of layout schemes.
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3 27 Design Space Exploration Coarse-grained architectures can be tailored and optimized for different application domains. The goal is to design a domain-specific processor that provides just enough flexibility for that domain while minimizing the energy consumption for a given level of performance. Achieving this goal requires numerous architectural choices and finding the optimal architecture involves many trade-offs in choosing values for each parameter. To support the finding of a suitable CGRA for a given application domain, the architecture exploration flows have been suggested in [7, 8, 21, 31, 38, 54–56, 60, 63].
Instead of a data cache, data is streamed in directly from external memory or sensors. Instead of an instruction cache, programmed controllers generate a small instruction stream which is decoded as it flows in parallel with the datapath. Instead of a global register file, data and intermediate results are stored locally in registers and small RAMs, close to their destination functional units. Instead of a crossbar, a programmable interconnect is configured to forward data between specific functional units on a per application basis.
6 mm2 . 65 million. The chip has 132 pins, which includes a 72-pin data interface, 5-bit test interface and 53 pins for power and ground. 8V supplies for the I/Os and core, respectively. The core area is divided into two areas: (1) the fabric, and (2) the virtualization and interface logic. The fabric consists of sixteen stripes. The virtualization and interface logic is implemented using standard cells. The configuration data is stored in 22 SRAMs, each with 256 32-bit words. Four 256 word by 32-bit dual-port SRAMs are used for storage of state information in the fabric.