By Ashenden P. J.
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Additional resources for The VHDL Cookbook
Example text
After the leading edge of phi1 during the subsequent T1 state, the processor negates fetch and asserts write. The read signal remains false for the whole transaction. During the T1 state, the processor also makes the data to be written available on the data bus. The memory 7. Sample Models: The DP32 Processor Ti 7-5 T1 T2 Ti phi1 phi2 valid address a_bus valid fetch fetch read write valid data in d_bus ready Figure7-4. DP32 bus read transaction. Ti T1 T2 Ti phi1 phi2 a_bus valid address fetch read write d_bus valid data out ready Figure7-5.
Finally an example of an entity declaration with no generic constants or TEST_BENCH Y Z TG A A B B Y DUT Z Figure 3-1. Test bench circuit. 3. VHDL Describes Structure 3-3 ports: entity test_bench is end test_bench; Though this might at first seem to be a pointless example, in fact it illustrates a common use of entities, shown in Figure3-1. A top-level entity for a design under test (DUT) is used as a component in a test bench circuit with another entity (TG) whose purpose is to generate test values.
A block configuration for data_path could be specified as shown in Figure5-4. Alternatively, if the library also contained a configuration called alu_struct for an architecture structure of the entity alu_cell, then the block configuration could use this, as shown in Figure5-5. 5. alu_cell(behaviour) generic map (width => 32) port map (function_code => function, operand1 => op1, operand2 => op2, result => result, flags => open); end for; other configuration items end for; Figure5-4. Block configuration using library entity.