By Boris Murmann
With the appearance of robust electronic sign processing in transportable digital functions, we've seen a becoming, unhappy call for for energy effective, high-speed and high-resolution analog-to-digital converters (ADCs). whereas expertise scaling has resulted in innovative earnings in electronic computing strength and effort potency, development in analog-to-digital conversion interfaces has been relatively gradual. Digitally Assisted Pipeline ADCs: concept and Implementation explores the chance to minimize ADC energy dissipation via leveraging electronic sign processing functions in fantastic line built-in circuit know-how. The defined digitally assisted pipelined ADC makes use of a statistics-based procedure id strategy as an allowing aspect to exchange precision residue amplifiers with basic open-loop achieve phases.
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Additional info for Digitally Assisted Pipeline ADCs: Theory and Implementation
Again, this choice is somewhat arbitrary, but fairly reasonable. As we see from these four data points, energy efficiency in noise limited circuits is virtually constant, and independent of technology. 3 Pipelined ADC Performance Trends We now compare the above result to FOM3 performance from published works. As an example, we use data from 10-bit pipelined ADCs, which is summarized in Table 3-2 and plotted in Figure 3-18 versus feature size. 5 years. 6 years. Table 3-2. 10-bit pipelined ADC performance.
To investigate this, we are showing the ratio tslew/tlin in Figure 3-16 for N=10 and G=2. A gain of G=2 is often used in pipeline stages to maximize their operating speed. 25µm 0 0 50 100 150 fs [MHz] 200 250 300 Figure 3-16. Ratio slewing/linear settling time vs. sampling speed. 18µm technology until about fs=125MHz. 18µm. It is now interesting to modify FOMPSD to include the slewing effect. Using (3-25) and (3-26) we can rewrite the speed portion of (3-20) to get t slew t lin v . § g m · ¸¸ V DD ¨¨ © I D ¹ ( fT ) 1 FOM PSD (3-27) We now plot this new figure of merit versus a new, effective sampling frequency that also captures the additional settling time due to slewing (see Figure 3-17).
However, in high dynamic range circuits it is usually true that Cgs<